Semiconductor device

ABSTRACT

There is provided a large capacity memory such as a DRAM and an SDRAM in which bonding pads PS and PD are put not at the center but aside between memory array regions UL and UR disposed on the upper side of a four-bank structure of banks  0  through  3  and memory array regions DL and DR disposed on the lower side firstly. Secondly, the disposition of the bonding pads Ps and PD is staggered on the right and left and the right half bonding pads PD are shifted up by about 30 μm. Only a sense amplifier, a column decoder and a main amplifier which need to be approached to the memory array regions DL and DR are disposed between the bonding pads PS and PD and the lower memory array regions DL and DR and indirect peripheral circuits are disposed on the upper side of the bonding pads PS and PD.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a technology for laying out semiconductor devices and more specifically to a technology effectively applicable to the disposition of pads for efficiently laying out a large capacity memory such as a DRAM and a synchronous DRAM (SDRAM).

[0002] The technological problem in DRAMs and SDRAMs which the inventor has examined is that a number of bits tends to be multiplied from ×4 to ×16 and ×32 and a number of pads tends to be also increased. For instance, while a number of input/output pins in a 64 M-bit DRAM (×4, ×8 and ×16 have been realized by bonding option) is 54 in the package, the DRAM requires about 70 pads as internal pads including normal signal pads such as address, clock and data signal pads, power source pads, experimental pads and bonding option pads (for switching ×4 through ×16 and switching a number of banks). It also requires pad dimensions and spaces therebetween and it has become difficult to array in a row for the LOC method gradually in the shrink generation. Even if they can be arrayed in a row, it has become difficult to assure large channel and power source bus regions between their gap.

[0003] A step-down system or a voltage regulator is often adopted in the late high integrated memories, so that a variety of power source lines are required within a chip. They include VDD, VSS, VDDQ and VSSQ as the external power source lines and VPERI (for a peripheral circuit), VDL (for a memory array), VPP (for a boost word driver) and VBB (for biasing an array substrate) as the internal power source lines. Still more, the power source lines may be divided into those for the memory arrays (VDDA, VSSA), for the general peripheral circuits (VDD, VSS) and for the input circuits (VDDI, VSSI) as measures to counter noises. Thus, it has become difficult to dispose the pads adequately due to the increase of the pads owing to the multiplication of bits and the variety of power source lines have come to be required due to the high integration in the memories such as the DRAM and SDRAM.

[0004] It is noted that as the technology related to the large capacity memories such as the DRAM and SDRAM, the technology described in “Advanced Electronics I-9, Super LSI Memory” published by Baifukan Co., Ltd. on Nov. 5, 1994, may be cited for example.

[0005] Japanese Patent Laid-Open No. 116865/1991 has disclosed a semiconductor memory device in which direct peripheral circuits are disposed in a region between two memory cell arrays along the respective memory cell arrays, in-direct peripheral circuits are disposed in a region between the direct peripheral circuits along one direct peripheral circuit, external terminals are disposed in the region between the direct peripheral circuits along the other direct peripheral circuit and a substrate voltage generating circuit is disposed in a region between the indirect peripheral circuit and the external terminal.

[0006] U.S. Pat. No. 5,579,256 (corresponding Japanese Patent Laid-Open No. 134568/1998) has disclosed a semiconductor device in which bonding pads, a voltage converter, a substrate voltage generating circuit and others are disposed at the center part of the chip.

[0007] U.S. Pat. No. 5,473,198 (corresponding Japanese Patent Laid-Open No. 350052/1994) has disclosed a semiconductor device in which axially symmetrical data input/output pads are disposed in two rows in parallel at the center part of the semiconductor chip.

[0008] U.S. Pat. 5,640,362 (corresponding Japanese Patent Laid-Open No. 128973/1997) has disclosed a synchronous semiconductor memory device having a plurality of data input/output pad groups 20 positioned at the right and left sides based on the center of a semiconductor chip 100, disposed in a row horizontally between upper and lower memory bank arrays 0 through 7 and having the same number with the memory array banks 0 through 7 to input/output information to/from the memory array banks 0 through 7.

[0009] U.S. Pat. No. 5,619,472 (corresponding Japanese Patent Laid-Open No. 139287/1996) has disclosed a center pad disposed type semiconductor memory device in which an IO pad array, i.e., a first pad array, is disposed between a core block 1 and a core block 2 and an address pad array, i.e., a second pad array, is disposed between a core block 3 and a core block 4.

[0010] U.S. Pat. No. 5,627,792 (corresponding Japanese Patent Laid-Open No. 125143/1996) has disclosed a semiconductor memory device in which respective pins (power souce pins, ground pins, data input/output pins, control system signal pins, address system signal pins) of a lead frame are connected to bonding pad groups disposed along a center line in the center part of a semiconductor substrate by bonding wires 55.

SUMMARY OF THE INVENTION

[0011] Noticing on the regularity of the disposition of standard pins in the large capacity memory such as the DRAM and SDRAM as described above, the inventor has examined an efficient layout of the pads and the so-called indirect peripheral circuits (except of the direct peripheral circuits such as memory cells, sense amplifiers and decoders) conforming to that. The contents which the inventor has examined will be explained below with reference to FIGS. 8 and 9.

[0012] The disposition of the standard pins of the DRAM and SDRAM will be considered at first. FIG. 8 shows the disposition of the pins of a 64 M SDRAM. As shown in the figure, data signal pins (DQ*) exist at the upper half of the chip in the figure and address and clock signal system pins (A*, CLK, CKE, /RAS, /CAS etc.) exist at the lower half. This circumstance is the same also in an EDO DRAM other than the SDRAM. Considering this by turning the chip by 90 degrees, it means from the point of view in designing the chip that the data signal system circuits exist at the right half of the chip and the address and clock signal system circuits exist at the left half. Thus, notching on the characteristics of the bonding pad groups and circuit groups whose properties are different, the inventor has considered of disposing them efficiently.

[0013]FIG. 9 shows the disposition of the conventional LOC assembling pads. The bonding pads PS and PD are disposed almost at the center of the indirect peripheral circuit region, electrostatic protecting elements and input/output circuits are disposed in the vicinity of the bonding pads PS and PD and internal circuits such as a control circuit and a pre-decoder are disposed between the regions at the both upper and lower sides of the bonding pads PS and PD and memory array regions UL, UR, DL and DR. Because the internal circuit groups are divided vertically by the bonding pads PS and PD in this disposition, it becomes difficult to exchange those large number of signals. Still more, there might be a problem when the circuit blocks are divided into the upper and lower parts that a power source line region is wasted because two sets of power source bus lines are required for them.

[0014] It is an object of the present invention to provide a semiconductor device of a large capacity memory such as a DRAM and SDRAM which allows an efficient layout of bonding pads and indirect peripheral circuits to be realized by taking wiring and size of electrostatic protecting elements and input/output circuits disposed in the vicinity of the bonding pads and of internal circuits disposed between the upper and lower regions of the bonding pads and the memory array regions.

[0015] The above and other objects as well as the novel characteristics of the invention will be apparent from the description of the present specification and from the accompanying drawings.

[0016] The typical ones of the inventions disclosed in the present application may be summarized as follows.

[0017] According to the inventive semiconductor device, bonding pad groups are put not at the center but aside to the upper or lower side between memory array regions firstly in disposing the pads in a large capacity memory such as a DRAM and an SDRAM having the large number of bonding pads. Secondly, the disposition of the bonding pads is staggered on the right and left and the right bonding pads on the data signal side are put back to the center more or less.

[0018] Because indirect peripheral circuits are disposed collectively on the other side in the semiconductor device described above according to the first feature, it allows a number of signals exchanged between the upper and lower sides by using the gap between the bonding pads to be reduced. It also requires only one set of power source buses necessary for the indirect peripheral circuits.

[0019] The second feature allows a large number of signal channels to be assured on the address and clock signal side. Although the data signal side requires not so many signal channels as compared to the address and clock signal side, large output transistors may be suitably placed adjoining the bonding pad thereabove and therebelow. While special power sources such as power sources dedicated for the output transistors are necessary on the data signal side additionally, they may be also suitably placed.

[0020] As a result, the indirect peripheral circuits may be laid out efficiently on the chip as a whole and the improvement of the speed may be achieved by the reduction of the chip area and the shortening of the signal passages.

[0021] A semiconductor device of the invention has a first edge (10-1) extending in a first direction; a second edge (10-2) facing to the first edge; a third edge (10-3) extending in a second direction perpendicular to the first edge; and a fourth edge (10-4) facing to the third edge; and further comprises an output circuit (22, 23); a first memory array (UR) disposed between the first edge and a first imaginary line (10-5); and a second memory array (DR) disposed between the second edge and the first imaginary line. In the semiconductor device, the plurality of pads (PD) are disposed on a second imaginary line (10-6); the first imaginary line is an imaginary line connecting a middle point (10-8) of the third edge and a middle point (10-9) of the fourth edge; the second imaginary line is an imaginary line which is parallel with the first imaginary line and which is imaginarily disposed between the first imaginary line and the second edge; the plurality of pads contain a first pad; the output circuit is connected with the first pad; the output circuit contains a first transistor (22) of a first conductive type and a second transistor (23) of a second conductive type; the first conductive type is different from the second conductive type; the first transistor is disposed between the first imaginary line and the first memory array; and the second transistor is disposed between the second imaginary line and the second memory array.

[0022] The above configuration allows a layout area for disposing the peripheral circuits to be largely prepared and an area occupied by the output circuits to be reduced. For instance, when the first and second transistors of the output circuit are PMOS and NMOS transistors, at least a part of a separating region for separating the PMOS and NMOS may be created by utilizing the lower part of the first pad connected to the output circuit. It then allows the area occupied by the output circuits to be reduced.

[0023] Another semiconductor device of the invention has a first edge extending in a first direction; a second edge facing to the first edge; a third edge extending in a second direction perpendicular to the first edge; and a fourth edge facing to the third edge; and further comprises a plurality of first pads (PD) to which data signals are supplied; a plurality of second pads (PS) to which address signals are supplied; a first memory array disposed between the first edge and a first imaginary line; and a second memory array disposed between the second edge and the first imaginary line. In the semiconductor device, the plurality of first pads are disposed on a second imaginary line; the plurality of second pads are disposed on a third imaginary line (10-7); the first imaginary line is an imaginary line connecting a middle point of the third edge and a middle point of the fourth edge; the second imaginary line is an imaginary line which is parallel with the first imaginary line and which is imaginarily disposed between the first imaginary line and the second edge; and the third imaginary line is an imaginary line which is parallel with the first imaginary line and imaginarily disposed between the second imaginary line and the second edge.

[0024] The above configuration allows the space for disposing the peripheral circuits such as an address buffer, an address decoder, data input/output circuits for inputting/outputting data signals and various voltage generating circuits to be prepared collectively and an area occupied by the circuits for outputting the data signals to be reduced. It also allows a large number of address signal lines to be disposed collectively.

[0025] A still other semiconductor device of the invention has a first edge extending in a first direction; a second edge facing to the first edge; a third edge extending in a second direction perpendicular to the first edge; and a fourth edge facing to the third edge; and further comprises a plurality of first pads; a plurality of second pads; a first memory array disposed between the first edge and a first imaginary line; and a second memory array disposed between the second edge and the first imaginary line. In the semiconductor device, the plurality of first pads are disposed on a second imaginary line; the plurality of second pads are disposed on a third imaginary line; the first imaginary line is an imaginary line connecting a middle point of the third edge and a middle point of the fourth edge; the second imaginary line is an imaginary line which is parallel with the first imaginary line and which is imaginarily disposed between the first imaginary line and the second edge; the third imaginary line is an imaginary line which is parallel with the first imaginary line and imaginarily disposed between the second imaginary line and the second edge; no pad exists between the plurality of first pads and the second edge; and no pad exists between the plurality of second pads and the first edge.

[0026] The above configuration allows the space for disposing the peripheral circuits such as an address buffer and an address decoder which receive address signals, data input/output circuits for inputting/outputting data signals and various voltage generating circuits to be prepared collectively and an area occupied by the circuits for outputting the data signals to be reduced. It also allows a large number of address signal lines to be disposed collectively. Further, because no pad exists between the plurality of first pads and the second edge and between the plurality of second pads and the first edge, many circuits may be disposed in this region and wires to be drawn around may be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIGS. 1(a) and 1(b) are schematic layouts and a partially enlarged view showing a semiconductor memory device according to one embodiment of the invention;

[0028]FIG. 2 is a schematic layout showing the disposition of bonding pads in the semiconductor memory device of the embodiment;

[0029]FIG. 3 is a schematic layout showing the disposition of circuit blocks at the center part of a chip in the semiconductor memory device of the embodiment;

[0030]FIG. 4 is a schematic layout showing the disposition of the bonding pads and power lines at the center part of the chip in the semiconductor memory device of the embodiment;

[0031]FIG. 5 is a circuit diagram showing the surrounding of the bonding pad for address and clock signals in the semiconductor memory device of the embodiment;

[0032]FIG. 6 is a circuit diagram showing the surrounding of the bonding pad for data signals in the semiconductor memory device of the embodiment;

[0033]FIG. 7 is a schematic plan view showing an LOC bonding method in the semiconductor memory device of the embodiment;

[0034]FIG. 8 is a diagram for explaining the disposition of input/output pins in a semiconductor memory device which is a precondition of the invention; and

[0035]FIG. 9 is a schematic layout showing the disposition of bonding pads in the semiconductor memory device which is the precondition of the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0036] An embodiment of the present invention will be explained in detail based on the drawings. It is noted that the same reference numerals denote the same members throughout the drawings for explaining the embodiment and their repeated explanation will be omitted.

[0037] FIGS. 1(a) and 1(b) are schematic layouts and a partially enlarged view showing a semiconductor memory device according to one embodiment of the invention, FIG. 2 is a schematic layout showing the disposition of bonding pads in the semiconductor memory device of the embodiment, FIG. 3 is a schematic layout showing the disposition of circuit blocks at the center part of a chip, FIG. 4 is a schematic layout showing the disposition of the bonding pads and power source lines at the center part of the chip, FIG. 5 is a circuit diagram showing the surrounding of the bonding pad of address and clock signals, FIG. 6 is a circuit diagram showing the surrounding of the bonding pad of data signals and FIG. 7 is a schematic plan view showing an LOC bonding method.

[0038] The structure of the schematic layouts of the semiconductor memory device of the present embodiment will be explained with reference to FIGS. 1a and 1 b at first.

[0039] The semiconductor memory device of the present embodiment is formed as a large capacity memory such as a DRAM and an SDRAM. Formed on one semiconductor chip 10 by the known semiconductor manufacturing technique are main row decoder regions 11, main word driver regions 12, column decoder regions 13, peripheral circuit and bonding pad regions 14, memory cell arrays 15, sense amplifier regions 16, sub-word driver regions 17, intersection regions 18 and others. In FIG. 1, the horizontal direction is the line direction (word line direction) and the vertical direction is the column direction (bit line direction).

[0040] In the large capacity memory, memory array regions composed of the memory cell arrays 15 and others are disposed by being divided into four banks 0 through 3 on the right and left side in the line direction and on the upper and lower sides in the column direction of the memory chip 10 as shown in FIG. 1 for example. The memory array regions disposed on the right and left sides are disposed in a pair while interposing the main row decoder region 11 disposed at the center via the main word driver regions 12.

[0041] The column decoder regions 13 corresponding to the memory array regions disposed at the upper and lower sides of the memory chip 10 are disposed at the center sides of the respective memory array regions. Row address buffers, column address buffers, pre-decoders, a timing generating circuit, data input/output circuits and others are disposed and bonding pads for connecting to the outside are provided further at the center thereof as the peripheral circuit and bonding pad regions 14.

[0042] In the memory array region, the sense amplifier regions 16 are disposed in the column direction of the memory cell arrays 15 while adjoining the memory cell array, the sub-word driver regions 17 are disposed in the line direction thereof while adjoining them, an FX driver (for driving the sub-word driver) and a control circuit of the sense amplifier group (such as a switching MOS transistor) are disposed in the intersection region 18 of the sense amplifier region 16 and the sub-word driver region 17. The word line is set in the line direction and the bit line is set in the column direction with respect to this memory cell array 15. It is apparent that the invention is applicable also when this disposition is reversed.

[0043] In the large capacity memory of the embodiment of the invention, the disposition of the bonding pads provided in the peripheral circuit and bonding pad regions 14 at the center of the memory array regions disposed at the upper and lower sides thereof is inventive. It will be explained below in order with reference to FIGS. 2 through 7.

[0044]FIG. 2 is a diagram showing the disposition of the bonding pads. Differing from one shown in FIG. 9, it has two characteristic points. Firstly, the bonding pads PS and PD are disposed not at the center but aside between the memory array regions UL and UR disposed on the upper side of the four banks of the banks 0 through 3 and the memory array regions DL and DR disposed on the lower side. They are put to the lower side in FIG. 2. Secondly, the disposition of the bonding pads PS and PD are staggered on the right and left. That is, the right-half bonding pads PD are shifted up from the bonding pads PS. The relative shift is around 30 μm. Only the sense amplifier, the column decoder and the main amplifier which need to be approached to the memory array regions DL and DR are disposed between the bonding pads PS and PD and the lower memory array regions DL and DR and the so-called indirect peripheral circuits are placed on the upper side of the bonding pads PS and PD.

[0045] Because the indirect peripheral circuits are disposed collectively on the upper side by shifting the bonding pads PS and PD to the lower side as a whole as the first characteristic point, a number of signals exchanged on the upper and lower sides of the bonding pads PS and PD is reduced remarkably as compared to the case of FIG. 9. Further, it requires to place only one set of power source buses which are necessary for the indirect peripheral circuits on the upper side. Although power sources for the column decoder and the main amplifier are necessary also on the lower side as a matter of course, they may be omitted because a large number of power sources are unnecessary on the lower side.

[0046] A large number of signal channels accompanying to X and Y address signal system and the control circuit may be assured in the indirect peripheral circuits on the left side by putting back the right bonding pads PD to the upper side more or less. While the input/output circuits accompanying to data occupy the most on the right side and require less signal channels as compared to the left side, it is preferable to shift the bonding pads PD to the upper side to place large output transistors while adjoining above and below the bonding pads PD. Further, while special power sources such as VDDQ and VSSQ dedicated for the output transistors are necessary additionally on the right side, they may be placed preferably.

[0047] For instance, as for the dimensions between the bonding pads PS and PD and the memory array regions UL, UR, DL and DR, when the interval T between the memory array regions UL and UR disposed on the upper side and the memory array regions DL and DR disposed on the lower side is around 700 μm, the bonding pads PS of the address and clock signal system on the left side are disposed while leaving a space TL of around 230 μm from the center and the bonding pads PD of the data signal system is disposed while leaving a space TR of around 200 μm from the center. No sense amplifier is included in the region of T, even though the main amplifier and the column decoder are included. The shift between the bonding pads PS and the bonding pads PD is around 30 μm. The bonding pads PS and bonding pads PD include voltage pads such as VDD and VSS.

[0048]FIG. 3 is an enlarged view of the center part of the chip. A well separation may be omitted and the positive side power source line may be shared by placing two indirect peripheral circuit groups so that PMOS transistors adjoin back to back. When a metallic three-layer wiring structure is adopted, a metallic first layer is used for connecting elements within the cell and the metallic second layer and the metallic third layer are used for coupling signals and power sources in the vertical (short edge) direction and the horizontal (long edge) direction, respectively in the long edge region between the upper and lower memory array regions UL, UR, DL and DR. It is because the metallic three-layer is thick and has the lowest resistance. Because the row decoder and main word driver regions between the memory array regions UL and UR and the memory array regions DL and DR is long in the vertical direction, the metallic three-layer wire is applied in the vertical direction.

[0049]FIG. 4 shows the power source lines at the center part of the chip. Names of a variety of power source lines are shown in the figure. VDDQ and VSSQ are the power sources dedicated for the output transistors, VSSI and VDDI are those for the input circuits, VDDA and VSSA are those for driving the sense amplifiers, VPERI is a step-down power source for the peripheral circuits, VDL is a power source for memory cell storage voltage and VPP is a power source for boosting the word line. Among these power source lines, the metallic two-layer and the metallic three-layer lines are used in the vertical and horizontal directions, respectively.

[0050]FIG. 5 shows the bonding pad PS for input signals. An electrostatic protecting element 21 is disposed on the bonding pad PS for the address and clock signals and the bonding pad PS is connected to an internal circuit via the electrostatic protecting element 21. The electrostatic protecting element 21 occupies a large area on one side of the bonding pad PS. A broken line in the figure implicates its approximate size.

[0051]FIG. 6 shows the bonding pad PD for data signals. An output PMOS transistor 22 and an output NMOS transistor 23 are disposed above and below the bonding pad PD. Gates of the output PMOS transistor 22 and the output NMOS transistor 23 are connected to the internal circuit. Broken lines in the figure implicate their approximate size. Differing from the bonding pad PS for the input signals shown in FIG. 5, the bonding pad PD requires large areas thereabove and therebelow.

[0052] When the bonding pads are to be disposed efficiently by noticing on the differences of the sizes and the wiring characteristics of the elements around the bonding pad PS in FIG. 5 and the bonding pad PD in FIG. 6, it is favorable to stagger the position of the bonding pads PS and PD up and down on the right and left sides thereof as shown in FIGS. 2, 3 and 4. Thus, the bonding pads PS and PD on the right and left sides are put on the lower side and the right bonding pads PD are disposed so as to be put back to the center more or less.

[0053]FIG. 7 is a plan view showing the state in which bonding has been implemented on an LOC (lead on chip) package. In the LOC package, a lead frame 31 is disposed above the memory chip 10 in the figure and the bonding pads PS and PD of the memory chip 10 are connected with the edge of the lead frame 31 by means of wire bonding by using wires 32 such as gold lines. The bonding may be implemented on the LOC package in the same manner with the conventional method because the bonding pads PS and PD deviate less from the whole memory chip 10 even if they are shifted. FIG. 7 shows the package corresponding to one shown in FIG. 8 in which a number of input/output pins is 54.

[0054] Therefore, according to the semiconductor memory device of the present embodiment, the indirect peripheral circuits are disposed collectively on the upper side by shifting the bonding pads PS and PD to the lower side as a whole, so that a number of signals exchanged between the upper and lower sides by using the gaps between the bonding pads PS and PD may be reduced. Further, it requires only one set of power source buses necessary for the indirect peripheral circuits. Still more, a large number of signal channels may be assured on the address and clock signal side by putting back the right bonding pads PD to the upper side more or less. Although the data signal side requires not so many signal channels as compared to the address and clock signal side, the large output PMOS transistor 22 and the output NMOS transistor 23 may be suitably placed above and below the bonding pad PD while adjoining it. The special power sources such as the VDDQ and VSSQ dedicated for the transistors 22 and 23 may be also suitably placed additionally. As a result, the indirect peripheral circuits may be efficiently laid out on the chip as a whole.

[0055] While the invention has been explained concretely based on the embodiment thereof, it is needless to say that the invention is not limited to the embodiment described above and may be variously modified within a scope of the spirit of the invention.

[0056] For instance, although the case of disposing the bonding pads by shifting to the lower side as a whole has been explained in the embodiment described above, the invention is not limited to such case and the bonding pads may be disposed by shifting to the upper side. It is preferable to dispose the data signal side bonding pads so as to be put back to the center more or less also in this case.

[0057] Further, although the case of the four bank structure in which the memory array region is composed of the banks 0 through 3 has been shown, the invention is applicable also to the other bank structure of eight banks for example. In such a case, the same effect may be obtained by disposing the bonding pads in the same manner as described above.

[0058] The effects obtained from typical ones of the invention disclosed in the present application may be summarized as follows:

[0059] (1) Because the indirect peripheral circuits may be disposed collectively on the other side by disposing the bonding pad groups not at the center but aside to the upper or lower side between the memory array regions, a number of signals exchanged between the upper and lower sides by using the gaps of the bonding pads may be reduced;

[0060] (2) Only one set of power source buses necessary for the indirect peripheral circuits needs to be placed by disposing the indirect peripheral circuits collectively on the other side by the effect (1) described above;

[0061] (3) A large number of signal channels may be assured on the address and clock signal side by staggering the disposition of the bonding pads on the right and left sides and by disposing the data signal side bonding pads so as to be put back to the center more or less;

[0062] (4) The large output transistors may be placed above and below the bonding pad while adjoining it on the data signal side by disposing the data signal side bonding pads so as to be put back to the center by the effect (3) described above;

[0063] (5) The special power sources such as the power sources dedicated for the output transistors may be disposed additionally by disposing the data signal side bonding pads so as to be put back to the center by the effect (3) described above; and

[0064] (6) Because the bonding pads and the indirect peripheral circuits may be efficiently laid out in the large capacity memory such as the DRAM and the SDRAM by the effects (1) through (5) described above, the speed may be improved by the reduction of the chip area and the reduction of the signal passages. 

We claim:
 1. A semiconductor device, wherein memory array regions are disposed in the peripheral part of a chip in the short edge direction and a large number of bonding pads are disposed along the long edge direction of said chip while putting aside to the upper or lower side from the center of the center part of said chip in the short edge direction; and said large number of bonding pads are disposed such that the shift to the upper or lower side from the center is different relatively at the left half portion and at the right half portion centering on the center part of said chip in the long edge direction.
 2. The semiconductor device according to claim 1, wherein said large number of bonding pads are disposed so as to be put aside to the upper or lower side from the center of the center part of said chip in the short edge direction and so that the shift to the upper or lower side from the center is large in an address and clock signal system and is small in a data signal system.
 3. The semiconductor device according to claim 2, wherein an electrostatic protecting element is disposed on one side of the upper and lower sides of said bonding pad of said address and clock signal system and output MOS transistors are disposed above and below said bonding pad of the data signal system.
 4. The semiconductor device according to claim 1, wherein said semiconductor device is a DRAM or a synchronous DRAM of 64 M bits or more.
 5. A semiconductor device, having: a first edge extending in a first direction; a second edge facing to said first edge; a third edge extending in a second direction perpendicular to said first edge; and a fourth edge facing to said third edge; said semiconductor device further comprising: an output circuit; a first memory array disposed between said first edge and a first imaginary line; a second memory array disposed between said second edge and said first imaginary line; and a plurality of pads being disposed on a second imaginary line, wherein said first imaginary line is an imaginary line connecting a middle point of said third edge and a middle point of said fourth edge, wherein said second imaginary line is an imaginary line which is parallel with said first imaginary line and which is imaginarily disposed between said first imaginary line and said second edge, wherein said plurality of pads comprises a first pad; said output circuit being connected with said first pad, wherein said output circuit comprises a first transistor of a first conductive type and a second transistor of a second conductive type, wherein said first conductive type is different from said second conductive type, wherein said first transistor is disposed between said second imaginary line and said first memory array, and wherein said second transistor is disposed between said second imaginary line and said second memory array.
 6. The semiconductor device according to claim 5, wherein said first and second transistors are MOS transistors.
 7. The semiconductor device according to claim 6, wherein said first conductive type is P-type and said second conductive type is N-type.
 8. The semiconductor device according to claim 6, wherein said output circuit comprises an inverter circuit having an output terminal connected to said first pad and said inverter circuit comprises said first and second transistors.
 9. The semiconductor device according to claim 5, wherein said first pad, said first transistor and said second transistor are disposed on a third imaginary line and said third imaginary line extends in the direction perpendicular to said first imaginary line.
 10. The semiconductor device according to claim 5, wherein said first memory array and said second memory array contain a dynamic type memory cells.
 11. The semiconductor device according to claim 5, wherein said first edge is longer than said third edge.
 12. The semiconductor device according to claim 5, wherein the centers of said plurality of pads are disposed on said second imaginary line.
 13. The semiconductor device according to claim 5, wherein each of said plurality of pads is quadrilateral and a point where two diagonal lines of said quadrilateral intersect is disposed on said second imaginary line.
 14. The semiconductor device according to claim 5, wherein the centers of balance of said plurality of pads are disposed on said second imaginary line.
 15. A semiconductor device, having: a first edge extending in a first direction; a second edge facing to said first edge; a third edge extending in a second direction perpendicular to said first edge; and a fourth edge facing to said third edge; said semiconductor device further comprising: a plurality of first pads to which data signals are supplied; a plurality of second pads to which address signals are supplied; a first memory array disposed between said first edge and a first imaginary line; and a second memory array disposed between said second edge and said first imaginary line, wherein said plurality of first pads are disposed on a second imaginary line, wherein said plurality of second pads are disposed on a third imaginary line, wherein said first imaginary line is an imaginary line connecting a middle point of said third edge and a middle point of said fourth edge, wherein said second imaginary line is an imaginary line which is parallel with said first imaginary line and which is imaginarily disposed between said first imaginary line and said second edge, and wherein said third imaginary line is an imaginary line which is parallel with said first imaginary line and imaginarily disposed between said second imaginary line and said second edge.
 16. The semiconductor device according to claim 15, wherein said plurality of first pads are disposed between a fourth imaginary line and said third edge; said plurality of second pads are disposed between said fourth imaginary line and said fourth edge; and said fourth imaginary line is an imaginary line connecting the middle point of said first edge and the middle point of said second edge.
 17. The semiconductor device according to claim 15, wherein said first edge is longer than said third edge.
 18. The semiconductor device according to claim 15, wherein the centers of said plurality of second pads are disposed on said second imaginary line; and the centers of said plurality of second pads are disposed on said third imaginary line.
 19. The semiconductor device according to claim 15, wherein each of said plurality of first pads is quadrilateral and a point where two diagonal lines of said quadrilateral intersect is disposed on said second imaginary line; and each of said plurality of second pads is quadrilateral and a point where two diagonal lines of said quadrilateral intersect is disposed on said third imaginary line.
 20. The semiconductor device according to claim 15, wherein the centers of balance of said plurality of first pads are disposed on said second imaginary line; and the centers of balance of said plurality of second pads are disposed on said third imaginary line.
 21. A semiconductor device, having: a first edge extending in a first direction; a second edge facing to said first edge; a third edge extending in a second direction perpendicular to said first edge; and a fourth edge facing to said third edge; said semiconductor device further comprising: a plurality of first pads; a plurality of second pads; first memory array disposed between said first edge and a first imaginary line; and a second memory array disposed between said second edge and said first imaginary line, wherein said plurality of first pads are disposed on a second imaginary line, wherein said plurality of second pads are disposed on a third imaginary line, wherein said first imaginary line is an imaginary line connecting a middle point of said third edge and a middle point of said fourth edge, wherein said second imaginary line is an imaginary line which is parallel with said first imaginary line and which is imaginarily disposed between said first imaginary line and said second edge, wherein said third imaginary line is an imaginary line which is parallel with said first imaginary line and imaginarily disposed between said second imaginary line and said second edge, wherein no pad exists between said plurality of first pads and said second edge, and wherein no pad exists between said plurality of second pads and said first edge.
 22. The semiconductor device according to claim 21, wherein said plurality of first pads are disposed between a fourth imaginary line and said third edge; said plurality of second pads are disposed between said fourth imaginary line and said fourth edge; and said fourth imaginary line is an imaginary line connecting the middle point of said first edge and the middle point of said second edge.
 23. The semiconductor device according to claim 22, wherein said plurality of first pads receive data signals and said plurality of second pads receive address signals.
 24. The semiconductor device according to claim 21, wherein said plurality of first pads receive data signals from the outside of said semiconductor device and said plurality of second pads receive address signals from the outside of said semiconductor device.
 25. The semiconductor device according to claim 21, wherein said first edge is longer than said third edge.
 26. The semiconductor device according to claim 21, wherein the centers of said plurality of second pads are disposed on said second imaginary line and the centers of said plurality of second pads are disposed on said third imaginary line.
 27. The semiconductor device according to claim 21, wherein each of said plurality of first pads is quadrilateral and a point where two diagonal lines of said quadrilateral intersect is disposed on said second imaginary line; and each of said plurality of second pads is quadrilateral and a point where two diagonal lines of said quadrilateral intersect is disposed on said third imaginary line.
 28. The semiconductor device according to claim 21, wherein the centers of balance of said plurality of first pads are disposed on said second imaginary line; and the centers of balance of said plurality of second pads are disposed on said third imaginary line. 